This invention relates generally to FinFETs (Field Effect Transistors, FETs, with fins) and, more specifically, relates to preventing fin erosion and limiting EPI (epitaxial) overburden in FinFETs.
At the end of this disclosure, a list of abbreviations is presented. This list contains many of the abbreviations used herein and in the drawing figures.
FIN erosion during RIE to form a first set of spacers (“spacer1”) on a gate of the FinFET is one of the key issues in SOI FinFET. Fin attack during the spacer pull down leads to a reduction in active carrier dose and increased access resistance. That is, spacer pull down is the removal (e.g., via RIE) of the spacer material so that the spacer material is left as a spacer on a side of the gate. The RIE is isotropic, so spacer pull down can over etch certain areas. Thus, the RIE for this pull down typically also attacks the Si fins, such that the fin height in the S/D areas is lower than the fin height in the gate region (as the fins are protected at least by the gate material in the gate region). The removal of material from the Si fins in the S/D regions leads to the reduction in active carrier dose and increased access resistance. Hardware data suggests by minimizing the Si loss to the fins in the source/drain regions, Ieff (effective switching current) improves with Rext (external resistance) reduction.
Besides, it is critical to reduce the epitaxial overgrowth on top of the fin in the SD region. Excess epitaxial overburden occurs when lateral growth of Si from the sides of the fins to create merged fins also causes vertical growth of Si from the top of the fins. Excess epitaxial overburden leads to increase of fringing capacitance from PC (e.g., gate) to the epitaxial overgrowth. The overburden also affects a profile of a second set of spacers (“spacer2”) on the gate and may lead to shorts from the gate to the S/D regions.